1. The Field of the Invention
The present invention relates to a pattern memory circuit for an integrated circuit testing apparatus.
2. Prior Art
When a fault in an integrated circuit testing apparatus, especially a functional fault as appearing as an abnormalcy in the waveform of its input or output signal, is found, the test is interrupted and the abnormalcy is checked by using an independent sequence program for checking pattern memory operation. However, as the contents of the test pattern are rewritten by the memory checking it is required to cause the actual test pattern data to take temporary shelter to a CPU and, after completion of the memory check, the test pattern data are transferred back to the test pattern memory.
Next, a construction of the conventional pattern memory circuit for integrated circuit testing apparatus will be described by making reference to FIG. 6. In this figure, 1 is CPU, 2 is an address generating circuit, 3 is a data generating circuit, 9 is a comparator and 11 is a pattern memory.
In operation of the pattern memory circuit of FIG. 6, a sequence program for memory checking is written in the CPU 1 beforehand and, during a write mode, any desired address is given from the CPU 1 to the address generating circuit 2. The address generating circuit 2 receives the given address and supplies it to input terminal of the pattern memory 11. The data generating circuit 3 receives a data from the CPU 1 and supplies it to a data input terminal of the pattern memory 11. The data is written in the pattern memory 11 at the designated address.
Next, during a read mode, a desired address of the pattern memory 11 from which the data is to be read out is given from the CPU 1 to the address generating circuit 2, which, in turn, gives the address to the pattern memory 11 as an address input. The pattern memory read out a date from the given address and sends it to the comparator 9. The data generating circuit 3 is given an expected data from the CPU 1 and sends it to the the comparator 9, in which the output data of the pattern memory and the expected data are compared with each other and the comparator makes a decision as to whether the pattern memory 11 is consistent or not.